Prodigy PGY-I3C-EX-PD I3C Protocol Exerciser and Analyzer

Exerciser:

Configurable: 1 Master + 3 Slaves or 1 Secondary Master + 2 Slaves

I3C / I2C Traffic Generation: Custom I3C / I2C traffic generation (Simulate real world network traffic)

SCL Frequency: 1Hz to 12.5MHz. Note: Prodigy device supports up to 10MHz at 1V frequency as a slave

Configurable Voltage Level Drive: 0.9V to 3.4V

Steps: 0.9 – 1.27 V (In steps of 5mV)

1.27 – 1.95V (In steps of 10mV)

1.95 - 3.4V (In steps of 30mV)

Hot Join: Yes, supported

IBI: Yes, supported

CCC Support:

+ All CCC are supported in Master slide. 

+ All CCC are supported in Slave except SETXTIME, ENTTM, ENTAS*

SCL Duty Cycle variation: User Defined (In Fine resolutions of 10ns)

SCL & SDA Delay: User Defined (In Fine resolutions of 18ps)

Delay between two messages: User Defined (In Fine resolutions of ns, us, ms and seconds)

Error injection:

S0 to S5 types of errors specified in I3C specifications.

CRC errors in DDR traffic.

Preamble errors in DDR traffic ACK / NACK Errors (Slave) Master Abort.

Non-Standard Frames.

Non-Standard Start, Stop and HDR exit patterns, slave reset Save and Load Scripts. 

API Support: Support for Automation of operation using Python or C++

Protocol Analysis:

Supports: I3C & I2C protocol decode

Protocol Views: Timing Diagram View;  Protocol Listing View; Bus-Diagram to display Protocol packets with timing diagram plot

Protocol Trigger: 

+ Auto (Trigger on any packet)

+ Simple (Trigger on user defined I3C or I2C packet)

+ Advanced (Multi-state & multi-level trigger with timer capability)

Capture Duration: Continuous streaming Protocol Data to host HDD/SSD

Protocol Error Report:

+ S0 to S5 types of errors specified in the I3C specifications

+ CRC errors in DDR traffic

+ Preamble errors in DDR traffic ACK /NACK Errors (Slave) Master Abort

+ Non-Standard frames

+ Non-standard Start, Stop and HDR exit patterns.

Host Connectivity: USB 3.0 / 2.0 interface